IIDG Fault Current Analysis and Calculation Considering Voltage Amplitude Detection Delay and Phase Jump

doi:10.11930/j.issn.1004-9649.202212094

Abstract

Abstract:

The volatility, weak feedback, and strong control of inverter interfaced distributed generation (IIDG) make it have different short-circuit current characteristics from synchronous generators under faults, and accurate analysis of them is the basis for the analysis of relay protection adaptability and the research of new protection principles, which is of great significance. Since the existing literature ignores the voltage amplitude detection delay and makes it difficult to accurately analyze the fault characteristics of IIDG, this paper takes the three-phase short circuit of the new energy transmission line as an example, comprehensively considers the influence of the voltage amplitude detection delay and the dynamic response characteristics of the phase-locked loop caused by phase jump, and finely divides the transient process of IIDG fault. It also establishes the fault current analysis expression under voltage and current loop control and current loop control for the two stages of the transient process of the fault. The influence mechanism of voltage detection delay and dynamic response of phase-locked loop on the transient characteristics of IIDG fault current is clarified. Finally, based on the Matlab/Simulink simulation platform, the correctness of the fault current analysis and calculation model proposed in this paper is verified.

Key words: inverter interfaced distributed generation, current analysis and calculation, amplitude detection delay, phase jump, symmetric fault

Meiling LUO, Ying MA, Weibing HUANG, Lingkun MENG, Xiaojun YU, Tao ZHENG. IIDG Fault Current Analysis and Calculation Considering Voltage Amplitude Detection Delay and Phase Jump[J]. Electric Power, 2024, 57(2): 72-81.

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URL: https://www.electricpower.com.cn/EN/10.11930/j.issn.1004-9649.202212094

https://www.electricpower.com.cn/EN/Y2024/V57/I2/72

Figures/Tables 14

Fig.1 IIDG grid-connected system topology and control block diagram

Fig.2 Structure of phase-locked loop control

Fig.3 Voltage drop at grid-connected point

Fig.4 Phase change of phase-locked loop output

Fig.5 Path affected by phase-locked loop

Fig.6 Fault current analysis

Fig.7 IIDG grid-connected structure

Table 1 IIDG grid-connected simulation model parameters

参数	数值	参数	数值
额定容量/(MV·A)	0.25	变压器T1变比	0.38/35
电压环控制参数$ {K}_{\mathrm{v}\mathrm{p}} $	2	变压器T2变比	35/110
电压环控制参数$ {K}_{\mathrm{v}\mathrm{i}} $	400	滤波电感/mH	20
电流环控制参数$ {K}_{\mathrm{i}\mathrm{p}} $	0.3	滤波电阻/mΩ	0.37
电流环控制参数$ {K}_{\mathrm{i}\mathrm{i}} $	20	直流母线电容/μF	8000
锁相环控制参数K_p	180	锁相环控制参数K_i	3200

Fig.8 Voltage drop waveform at grid-connected point (dropped to 0.8 p.u.)

Fig.9 Comparison between current of dq axis theory and simulation (voltage of grid-connected point dropped to 0.8 p.u.)

Fig.10 Comparison between A phase theory and simulation current (voltage of grid-connected point dropped to 0.8 p.u.)

Fig.11 Voltage drop waveform at grid-connected point (dropped to 0.45 p.u.)

Fig.12 Comparison between current of dq axis theory and simulation (voltage of grid-connected point dropped to 0.45 p.u.)

Fig.13 Comparison between A phase theory and simulation current (voltage of grid-connected point dropped to 0.45 p.u.)

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